This invention relates to a mode detection circuit in a liquid crystal displays (LCDs), and more particularly to a mode detection circuit in LCDs capable of changing the priority operation mode and preventing malfunction due to a noise.
Recently, there are a data only enable mode and a data enable/synchronous mode as the operation mode of LCD modules according to notebook computer manufacturers. In the data only enable mode, only data enable signal DE is provided as a control signal and in the data enable/synchronous mode, a vertical synchronous signal Vsync and the data enable signal are provided as a control signal.
The prior LCD module has a disadvantage in that the operation mode is manually selected according to its input signals. So as to solve the problem, the method is suggested that sets an initial mode in advance and detects the input signals based on the initial mode and then changes the operation mode based on the detection of the input signal. This is, the method gives priority to the initial mode and changes the corresponding operation mode by detecting the input signals of the priority mode or the another mode which are externally provided. The method is capable of changing to the desired mode from the initial mode of the priority mode. However, when the LCD module malfunctions due to the noise mixed to the input signals, it should be fixed to the operation mode by using an external pin so that the automatic mode change does not accomplished.
It is an object of the present invention to provide a mode detection circuit in LCDs which automatically selects the priority operation mode thereof according to the mode selection signal as well as changes the operation mode according to its external input signals.
It is an aspect of the present invention to provide a mode detection circuits in LCDs, comprising: a first mode signal detection means for detecting an enable/synchronous signal mode in response to a vertical synchronous signal and for generating a first mode detection signal; a second mode signal detection means for detecting an enable mode signal based on a data enable signal and a clock signal and for generating a second mode detection signal; a mode selection means for selecting one of a first mode detection signal and a second mode detection signal from the first mode signal detection means and the second mode signal detection means in response to a mode selection signal and for providing the selected mode detection signal as a mode determining signal.
The first mode signal detection means includes: a vertical synchronous signal detection means for detecting the vertical synchronous signal and for generating the vertical synchronous detection signal; and a first mode detection signal generation means for generating the first mode detection signal from the vertical synchronous detection signal generated from the vertical synchronous signal detection means.
The vertical synchronous signal detection means includes: a first counter means for countering the vertical synchronous signal; and a first decoder means for receiving an output of the first counter portion and for confirming whether the vertical synchronous signal is regularly supplied by decoding the output of the first counter portion, or not and for generating the vertical synchronous detection signal to the first mode detection signal generation means.
The counter means includes; a first D flip flop which is triggered at a negative edge of the vertical synchronous signal and an output thereof is fed back to an input thereof through a first inverter; a second D flip flop which is triggered at a positive edge of the output of the first D flip flop and an output thereof is fed back to an input thereof through a second inverter; and a thirdd flip flop which is triggered at a positive edge of the output of the second D flip flop and an output thereof is fed back to an input thereof through a third inverter. The decoder means includes a first AND gate which receives the output of the first and third D flip flops and an inverted output of the second D flip flop and provides an output thereof as a vertical synchronous detection signal to the first mode detection signal generation means.
The first mode detection signal generation means a fourth D flip flop which is triggered at a positive edge of the vertical synchronous detection signal and receives a power voltage as an input and provides an inverted output thereof as the first mode detection signal.
The second mode signal detection means includes: a pseudo vertical synchronous signal generation means for generating a pseudo vertical synchronous signal similar to the vertical synchronous signal based on the data enable signal and the clock signal; an enable signal detection means for detecting the enable signal from the pseudo vertical synchronous signal generated from the pseudo vertical synchronous signal generation means and for generating the enable detection signal; and a second mode detection signal generation means for generating the second mode detection signal from the enable detection signal generated from the enable signal detection means.
The pseudo vertical synchronous signal generation means includes a first D flip flop which is triggered at a negative edge of the clock signal and receives the data enable signal as an input signal and provides an output as the pseudo vertical synchronous signal.
The enable signal detection means includes a counter means for counting the pseudo vertical synchronous signal; and a second decoder means for confirming whether the pseudo synchronous signal is regularly supplied by decoding the output of the counter means, or not and for generating the enable detection signal to the second mode detection signal generation means.
The enable signal detection means includes: a first D flip flop which is triggered at a negative edge of the pseudo vertical synchronous signal and an output thereof is fed back to an input thereof through a first inverter; a second D flip flop which is triggered at a positive edge of the output of the first D flip flop and an output thereof is fed back to an input thereof through a second inverter; and a third D flip flop which is triggered at a positive edge of the output of the second D flip flop and an output thereof is fed back to n input thereof through a third inverter. The second decoder means an AND gate which receives the outputs of the first and the third D flip flops and an inverted output of the second D flip flops and provides an output thereof as an enable detection signal.
The second mode detection signal generation means a D flip flop which is triggered at a positive edge of the second decoder means and receives a power voltage as an input and provides an output as the second mode detection signal to the mode selection means.
The mode selection means includes a multiplexor for selecting one of the first mode detection signal from the first mode signal detection means and the second mode detection signal from the second mode signal detection means in accordance with the mode selection signal and providing the selected mode detection signal as the mode determining signal.
It is also provided to a mode detection circuit in a liquid crystal display, comprising: a first mode signal detection means for detecting an enable/synchronous signal mode in response to a vertical synchronous signal and for generating a first mode detection signal; a second mode signal detection means for detecting an enable mode signal based on a data enable signal and a clock signal and for generating a second mode detection signal; and a mode selection means for selecting one of a first mode detection signal and a second mode detection signal from the first mode signal detection means and the second mode signal detection means in response to a mode selection signal and for providing the selected mode detection signal as a mode determining signal; wherein in an initial state, the first mode signal detection means sets the second mode of data only enable mode and the second mode signal detection means sets the first mode of enable/synchronous mode.
It is still provided to a mode detection circuit in a liquid crystal display, comprising: a first mode signal detection means for detecting an enable/synchronous signal mode in response to a vertical synchronous signal and for generating a first mode detection signal, the first mode signal detection means includes a vertical synchronous signal detection means for detecting the vertical synchronous signal and for generating the vertical synchronous detection signal; and a first mode detection signal generation means for generating the first mode detection signal from the vertical synchronous detection signal generated from the vertical synchronous signal detection means; a second mode signal detection means for detecting an enable mode signal based on a data enable signal and a clock signal and for generating a second mode detection signal, the second mode signal detection means includes a pseudo vertical synchronous signal generation means for generating a pseudo vertical synchronous signal similar to the vertical synchronous signal based on the data enable signal and the clock signal; an enable signal detection means for detecting the enable signal from the pseudo vertical synchronous signal generated from the pseudo vertical synchronous signal generation means and for generating the enable detection signal; and a second mode detection signal generation means for generating the second mode detection signal from the enable detection signal generated from the enable signal detection means; and a mode selection means for selecting one of a first mode detection signal and a second mode detection signal from the first mode signal detection means and the second mode signal detection means in response to a mode selection signal and for providing the selected mode detection signal as a mode determining signal.